Wednesday, July 9, 2014
Performance enhancement with pipelining
Pipelines
With pipelining, the CPU begins executing a second instruction before the first instruction is completed. Pipelining results in faster processing because the CPU does not have to wait for one instruction to complete the machine cycle.
Pipelines
Pipelines in computers are used to improve the performance of the basic instruction cycle. The goal is to improve the throughput of the computer, the number of instructions per second (MIPS), by overlapping tasks in the instruction cycle. This technique is now used in all major computers.
A pipeline divides the operation of the instruction cycle into stages. Each stage:
• does one part of instruction cycle
• has its own dedicated hardware
• can run in parallel with the other stages
A 2-Stage Pipeline
A simple illustration of a pipeline can be made by considering what happens if we break the basic instruction cycle into two stages: a fetch stage and an execute stage. The timing diagram below comparesthe operation with and without this 2-stage pipeline.
With no pipeline (a) it takes 20 clock cycles to execute 10 instructions. With the 2-stage pipeline it takes 11 clock cycles, almost twice as fast. There is a small lost in performance as the pipeline fills but over many instructions this would be insignificant. Once the pipeline is full the 2-stage pipeline is two times faster. In general, the potential speedup is the number of stages.
Two-stage pipelines are not very common because most computer are trying to get even more improvement by using more stages. The PIC family of embedded microcontrollers is an example of a practical implementation a 2-stage fetch-execute pipeline.
More information
With pipelining, the CPU begins executing a second instruction before the first instruction is completed. Pipelining results in faster processing because the CPU does not have to wait for one instruction to complete the machine cycle.
Pipelines
Pipelines in computers are used to improve the performance of the basic instruction cycle. The goal is to improve the throughput of the computer, the number of instructions per second (MIPS), by overlapping tasks in the instruction cycle. This technique is now used in all major computers.
A pipeline divides the operation of the instruction cycle into stages. Each stage:
• does one part of instruction cycle
• has its own dedicated hardware
• can run in parallel with the other stages
A 2-Stage Pipeline
A simple illustration of a pipeline can be made by considering what happens if we break the basic instruction cycle into two stages: a fetch stage and an execute stage. The timing diagram below comparesthe operation with and without this 2-stage pipeline.
With no pipeline (a) it takes 20 clock cycles to execute 10 instructions. With the 2-stage pipeline it takes 11 clock cycles, almost twice as fast. There is a small lost in performance as the pipeline fills but over many instructions this would be insignificant. Once the pipeline is full the 2-stage pipeline is two times faster. In general, the potential speedup is the number of stages.
Two-stage pipelines are not very common because most computer are trying to get even more improvement by using more stages. The PIC family of embedded microcontrollers is an example of a practical implementation a 2-stage fetch-execute pipeline.
More information
Control Unit
• A microprogram has a sequence of instructions in a microprogramming language.
– These are very simple instructions that specify micro‐operations.
Microprogrammed computers are characterized by the fact that the control signals are combined in control words, each bit of a word representing a control signal. The succession of the control words which indicate the correct sequence of elementary operations (micro-operations) that should be executed for each instruction is stored in a control memory. Each control word in the control memory represents a microinstruction, and it executes one or more micro-operations. The sequence of microinstructions form a microprogram.
A microprogrammed control unit has two main functions:
1. The control function, which defines the micro-operations that should be executed. This definition usually comprises the selection of the operands, selection of the operation to be executed, selection of the destination for a result, etc.
2. The sequencing function, which defines the address of the next microinstruction to be executed. This definition refers to identifying the source for the next address, controlling the test conditions, or generating the address value directly.
Micro‐instruction Types
• Each micro‐instruction specifies single (or few) micro‐operations to be performed
– (vertical micro‐programming)
• Each micro‐instruction specifies many different micro‐operations to be performed in parallel
– (horizontal micro‐programming)
More information
– These are very simple instructions that specify micro‐operations.
Microprogrammed computers are characterized by the fact that the control signals are combined in control words, each bit of a word representing a control signal. The succession of the control words which indicate the correct sequence of elementary operations (micro-operations) that should be executed for each instruction is stored in a control memory. Each control word in the control memory represents a microinstruction, and it executes one or more micro-operations. The sequence of microinstructions form a microprogram.
A microprogrammed control unit has two main functions:
1. The control function, which defines the micro-operations that should be executed. This definition usually comprises the selection of the operands, selection of the operation to be executed, selection of the destination for a result, etc.
2. The sequencing function, which defines the address of the next microinstruction to be executed. This definition refers to identifying the source for the next address, controlling the test conditions, or generating the address value directly.
Micro‐instruction Types
• Each micro‐instruction specifies single (or few) micro‐operations to be performed
– (vertical micro‐programming)
• Each micro‐instruction specifies many different micro‐operations to be performed in parallel
– (horizontal micro‐programming)
More information
Instruction Fetch Execute Cycle
1. Fetch Cycle
2. Decode Cycle
3. Execute Cycle
Working Of Instruction fetch Execute Cycle :
1.fetch an instruc:on from memory.
2.fetch any data required by the instruc:on from memory.
3.execute the instruc:on (process the data).
4.store results in memory.
5.go back to step (1)
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1. Fetch Cycle: The fetch cycle begins with retrieving the address stored in the Program Counter (PC). The address stored in the PC is some valid address in the memory holding the instruction to be executed. (In case this address does not exist we would end up causing an interrupt or exception).
The Central processing unit completes this step by fetching the instruction stored at this address from the memory and transferring this instruction to a special register – Instruction Register (IR) to hold the instruction to be executed. The program counter is incremented to point to the next address from which the new instruction is to be fetched.
2. Decode Cycle: The decode cycle is used for interpreting the instruction that was fetched in the Fetch Cycle. The operands are retrieved from the addresses if the need be.
3. Execute Cycle: This cycle as the name suggests , simply executes the instruction that was fetched and decoded.
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Detailed data path of a CPU
Central Processing Unit Introduction The CPU is made up of 3 major Components. The CPU performs a variety of functions dictated by the type of instructions that are incorporated in the computer In programming, memory locations are needed for storing pointers, counters, return addresses, temporary result , etc. Memory access is most time consuming operation in a computer. It is then more convenient and more efficient to store these intermediate values in processor registers, which are connected through common bus system. Control Register set ALU
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