Pipelines
With pipelining, the CPU begins executing a second instruction before the first instruction is completed. Pipelining results in faster processing because the CPU does not have to wait for one instruction to complete the machine cycle.
Pipelines
Pipelines in computers are used to improve the performance of the basic instruction cycle. The goal is to improve the throughput of the computer, the number of instructions per second (MIPS), by overlapping tasks in the instruction cycle. This technique is now used in all major computers.
A pipeline divides the operation of the instruction cycle into stages. Each stage:
• does one part of instruction cycle
• has its own dedicated hardware
• can run in parallel with the other stages
A 2-Stage Pipeline
A simple illustration of a pipeline can be made by considering what happens if we break the basic instruction cycle into two stages: a fetch stage and an execute stage. The timing diagram below comparesthe operation with and without this 2-stage pipeline.
With no pipeline (a) it takes 20 clock cycles to execute 10 instructions. With the 2-stage pipeline it takes 11 clock cycles, almost twice as fast. There is a small lost in performance as the pipeline fills but over many instructions this would be insignificant. Once the pipeline is full the 2-stage pipeline is two times faster. In general, the potential speedup is the number of stages.
Two-stage pipelines are not very common because most computer are trying to get even more improvement by using more stages. The PIC family of embedded microcontrollers is an example of a practical implementation a 2-stage fetch-execute pipeline.
More information
With pipelining, the CPU begins executing a second instruction before the first instruction is completed. Pipelining results in faster processing because the CPU does not have to wait for one instruction to complete the machine cycle.
Pipelines
Pipelines in computers are used to improve the performance of the basic instruction cycle. The goal is to improve the throughput of the computer, the number of instructions per second (MIPS), by overlapping tasks in the instruction cycle. This technique is now used in all major computers.
A pipeline divides the operation of the instruction cycle into stages. Each stage:
• does one part of instruction cycle
• has its own dedicated hardware
• can run in parallel with the other stages
A 2-Stage Pipeline
A simple illustration of a pipeline can be made by considering what happens if we break the basic instruction cycle into two stages: a fetch stage and an execute stage. The timing diagram below comparesthe operation with and without this 2-stage pipeline.
With no pipeline (a) it takes 20 clock cycles to execute 10 instructions. With the 2-stage pipeline it takes 11 clock cycles, almost twice as fast. There is a small lost in performance as the pipeline fills but over many instructions this would be insignificant. Once the pipeline is full the 2-stage pipeline is two times faster. In general, the potential speedup is the number of stages.
Two-stage pipelines are not very common because most computer are trying to get even more improvement by using more stages. The PIC family of embedded microcontrollers is an example of a practical implementation a 2-stage fetch-execute pipeline.
More information
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