Operations in the instruction set

The instruction set architecture (ISA)

defines how a computer appears to a machine language programmer or compiler. The ISA describes the (a) memory model, (2) instruction format, types and modes, and (3) operand registers, types, and data addressing. Instruction types include arithmetic, logical, data transfer, and flow control. Instruction modes include kernel and user instructions.Computing languages are translated from source code to assembly language to machine language



                   



  


The ISA is implemented using fetch-decode-execute cycle as shown in Figure 2.2. In fetch stage, operands are retrieved from memory. In decode stage; operands are converted into a format that ALU can manipulate. The execute stage performs the selected operation within the ALU. The control circuitry orderly routes data. Thus, in ISA cycle, operands are fetched from memory (fetch cycle), operands are converted into a format that ALU can accepts (decode cycle), and ALU performs selected operation on the decoded operands (execute cycle).

Machine language instructions are of four types: Arithmetic, Logical, Data transfer, and Control flow (branch), as follows:

•  Arithmetic: Addition, subtraction, multiplication, division
•  Logical: and, or, shift
•  Data transfer: load, store
•  Control:

           o Conditional - jump on equal, branch on not equal
           o Unconditional - jump
 

 Design Principles:

1. Simplicity favors regularity
    The instruction format is simple. For example, each instruction begins with an opcode that tells machine     
    what to do, follow by one to three operand symbols. Add a, b, c
2. Smaller is faster
3. Good design demands good compromises